1. Field of the Invention
The present invention relates generally to a dynamic memory device whose memory cells are each constructed by one transistor and one capacitor and are displaced from one another by 1/2.sup.n (n is a natural number equal to or larger than 2) pitch in a channel length direction, and more particularly to improvement of the layout of a conductive wiring layer on a memory cell array of the dynamic memory device.
2. Description of the Related Art
There have been known the dynamic memory devices of the type in which memory cells in a memory cell array are each constructed with one capacitor and one transistor. Some of this type of the memory devices employs such a memory cell array that are memory cells linearly arrayed on a first row are displaced by 1/2.sup.n (n is a natural number equal to or larger than (2) pitch from those in a second row as viewed in the channel length direction of the cell transistor. The memory device of this type is disclosed in Published Unexamined Japanese Patent Application No. 61-274357. The memory device in this gazette has a pattern as shown in FIG. 1.
Each capacitor is sandwiched by an element region 10 and a cell plate electrode 12 that is formed on a capacitor insulating layer layered on the element region 10. In use, the cell plate electrode 12 is common electrode for the memory cells. Each transistor is formed by a gate electrode 14 and diffusion layers (not shown) formed in the element region 10. The gate electrode 14 is layered on an insulating film (not shown) that is successively formed on the cell plate 10 and the element region 10. Groove portion 16 which is formed in a stepped configuration in position corresponding to the transistor region is arranged between adjacent cell plate electrode 12. Each word line 18 is coupled with the gate electrodes 14, through contact holes 20. In the dynamic memory device thus constructed, data are stored in the capacitors in the form of charge. The data is read out of the memory cell and applied to the bit line 22 through a contact 24 formed in the element region 10. The memory cell array thus constructed is advantageous in that since the minimum width "d" of the cell plate 12 may be selected to be relatively wide, if the cell size is reduced, the process to form the cell plate electrode 12 is easy.
In the above dynamic memory device, a bit line pair BL1 and BL1, a bit line pair BL2 and BL2, and sense amplifiers SA1 and SA2 are laid out as shown in FIG. 2. As shown, the bit line pair BL1 and is coupled with the sense amplifier SA1. The bit line pair BL2 and BL2 is coupled with the sense amplifier SA2. The bit line pair BL1 and BL1 and the bit line pair BL2 and BL2 are combined in an interdigitated fashion. One of the paired bit lines BL2 and BL2 is inserted between the paired bit lines BL1 and BL1. In the dynamic memory device of the 1/4 pitch type, such an interdigitated layout of the bit line pairs is essential. The memory device has another line, such as a column select signal line 26, extending along the bit lines.
Electrically, the layout of the bit lines may be modeled as shown in FIG. 3. In a layout that the signal line 26 is laid between the bit lines BL2 and BL1, as shown in FIG. 2, stray capacitances C.sub.F exist between the signal line 26 and the bit line BL2, and between the signal line 26 and the bit line BL1, as shown in FIG. 3. The stray capacitances in connection with the bit lines BL2 and BL1 are smaller than those in connection with the bit lines BL2 and BL1. In other words, the paired bit lines BL1 and BL1 are unbalanced in the stray capacitances that are caused by the presence of the signal line 26. Noise traveling through the signal line 26 is transferred through the stray capacitances to the paired bit lines in an imbalanced manner. The same thing is true for the paired bit lines BL2 and BL2.
An amplitude of the signal read out onto the bit line pairs is proportional to a ratio of a bit line capacitance to a memory cell capacitance, and is very small, several tens mV. The minute signal is differentially amplified by the corresponding sense amplifier, SA1 or SA2. A situation inevitably occurs that the noise is transferred to the paired bit lines through the stray capacitances in an imbalanced manner, before the minute signal is satisfactorily amplified by the sense amplifier. A difference between the imbalanced noise, called a coupling noise, together with the signal, is amplified by the amplifier, and grows. Extremely, the grown noise provides an improper data read operation. That is, the read out data is incorrect. The incorrect data read phenomenon due to the imbalanced stray capacitances is more distinguished in the memory devices of high speed and high integration density. As the integration density increases, the areal (lateral) and vertical (depth) dimensions of the memory device are reduced, so that the stray capacitances increase. If the frequency of a signal traveling through the signal line 26 is higher, the impedance by the stray capacitance is decreased, and hence the amount of noise transferred is also increased.